Applied Cryptography

Post-Quantum Cryptography

PQC

In the field of "applied cryptography", our chair deals with a wide variety of research topics. The post-quantum cryptography, which deals with the question of what secure cryptography can look like after the development of quantum computers, plays a major role in this. Our chair has been instrumental in advancing the implementation of Lattice-Based and Code-Based methods for hardware-based platforms. The challenge here is to implement the usually much larger methods on hardware suitable for IoT devices. In addition, side channel security against physical attacks by post-quantum methods also plays an important role in our research.



High-Performance Cryprography

In the field of "High-Performance Cryptography" our chair has made a significant contribution to the efficient implementation of elliptic curve arithmetic.

Effi­ci­ent El­lip­tic-Cur­ve Cryp­to­gra­phy using Cur­ve25519 on Reconfi­gura­ble De­vices

Effi­ci­ent El­lip­tic-Cur­ve Cryp­to­gra­phy using Cur­ve25519 on Reconfi­gura­ble De­vices, Pascal Sasdrich, Tim Gü­ney­su - 10th International Symposium on Applied Reconfigurable Computing (ARC'14), April 14-16, 2014, Vilamoura, Portugal.

Elliptic curve cryptography (ECC) has become the predominant asymmetric cryptosystem found in most devices during the last years. Despite significant progress in efficient implementations, computations over standardized elliptic curves still come with enormous complexity, in particular when implemented on small, embedded devices.
In this context, Bernstein proposed the highly efficient ECC instance Curve25519 that was shown to achieve new ECC speed records in software providing a high security level comparable to AES with 128-bit key. These very tempting results from the software domain have led to adoption of Curve25519 by several security-related applications, such as the NaCl cryptographic library or in anonymous routing networks (nTor). In this work we demonstrate that even better efficiency of Curve25519 can be realized on reconfigurable hardware, in particular by employing their Digital Signal Processor blocks (DSP). In a first proposal, we present a DSP-based single-core architecture that provides high-performance despite moderate resource requirements. As a second proposal, we show that an extended architecture with dedicated inverter stage can achieve a performance of more than 32,000 point multiplications per second on a (small) Xilinx Zynq 7020 FPGA. This clearly outperforms speed results of any software-based and most hardware-based implementations known so far, making our design suitable for cheap deployment in many future security applications.

  • The paper can be found here.
  • The source code can be found here.