Concurrent Error Detection Revisited – Hardware Protection against Fault and Side-Channel Attacks

Jan Richter-Brockmann, Pascal Sasdrich, Florian Bache, Tim Güneysu

The 15th International Conference on Availability, Reliability and Security (ARES 2020), August 25 - August 28, 2020, University College Dublin, Dublin, Ireland


Fault Injection Analysis (FIA) and Side-Channel Analysis (SCA) are considered among the most serious threats to cryptographic implementations and require dedicated countermeasures to ensure protection through the entire life-cycle of the implementations.

In this work, our contribution is twofold. First, we present a novel orthogonal layout of linear Error-Correcting Codes (ECCs) to adjust classical Concurrent Error Detection (CED) to an adversary model that assumes precisely induced single-bit faults which, with a certain non-negligible probability, will aff ect adjacent bits. Second, we combine our orthogonal error correction technique with a state-of-the-art SCA protection mechanism to demonstrate resistance against both threats.

Eventually, using AES as a case study, our approach can correct entirely faulted bytes while it does not exhibit detectable first-order side-channel leakage using 200 million power traces and Test Vector Leakage Assessment (TVLA) as state-of-the-art leakage assessment methodology. Furthermore, our hardware implementations reduce the area and resource consumption by 14.9 % – 18.3 % for recent technology nodes (compared to a conventional CED scheme).